In typical circuit design, circuit components are arranged to optimize space and/or circuit performance. Such arrangements can include the “layout” or pattern definition of each of the layers used in a semiconductor manufacturing process. For example, such layout can include metal interconnect or connectivity layers that are converted to masks or reticles for use in a wafer fabrication facility that manufactures ICs (i.e., “chips”).
While some circuits are designed using “custom” layout, others are designed using a partially or fully automated design flow. Application-Specific Integrated Circuit (ASIC) designs, as well as other functional blocks within a larger chip, such as System-On-Chip (SOC) designs, may employ custom and/or ASIC type flows on the same chip. In any event, typical ASIC flows use “place-and-route” tools for placing logic or circuit “blocks” and then “routing” or connecting the interface signals between the blocks. Such routing between circuit blocks is typically done using one or more metal connectivity layers for each signal path. In most modern ASIC designs, at least five layers of metal connectivity are employed.
In conventional place-and-route flows, circuit blocks or “cells” are first placed in desired locations and sized (i.e., adjust drive strength by changing transistor sizes and/or adding buffer stages) in accordance with a projected routing and capacitive load based on these desired cell locations. Then, signals are actually routed between the circuit blocks. A drawback of such an approach is that the cell sizing is done based on an estimated routing that typically provides capacitance values that are worse than the actual routing path. Referring now to FIG. 1, a conventional wire routing estimation approach is shown and indicated by the general reference character 100. Logic Function Implementation 102 can be any circuit block or cell that includes a driver stage to be sized in accordance with a resistance and capacitance (RC) load on Signal Path 104. Wire 106 can be a projected routed path or segment. Model Wire 108-1 can be an estimated wire route adjacent to (i.e., “above” or “below” on different routing layers or side-by-side on the same routing layer) Wire 106, contributing a capacitance C1. Similarly, Model Wire 108-2 can be another estimated wire route adjacent to Wire 106, contributing a capacitance C2. In essence, full coverage both above and below in different routing layers (and/or side-by-side on the same routing layer) would be assumed, making the capacitance estimate “worst case.”
Conventionally, the circuit blocks or “cells” are sized in accordance with such a worst case RC estimate. As a result, the cells may be sized too large for the actual routed signal paths and power consumption due to overdriven and non-optimal signal driving based on the actual load could be greater than necessary. Further, this problem gets worse as more advanced processes result in increased capacitance values.
For timing considerations, obtaining “timing closure” in conventional approaches may be more difficult due to the worst case estimates and this may further exacerbate the power consumption problem. Typically, capacitances of the actual resultant signal paths are extracted and provided to a simulator and/or timing closure tool. If the circuit meets the timing specifications for the design, timing closure has been obtained. However, if the circuit fails timing closure, adjustments to the circuit block placement and/or routing must be done. This process must be repeated until timing closure is met, delaying the completion of the overall design. In particular, overdriven signals resulting from such conventional solutions are susceptible to hold time violations. The signal paths must then be re-routed and/or the cells re-sized as part of one or more iterations in order to ultimately meet the timing constraints.
Given the increasing demands on circuit designers to more quickly create chips of increasing density, decreasing wire and transistor widths, and decreasing power supply and power consumption, it is difficult to ensure optimal cell sizing in an automated place-and-route flow. Increasing the complexity, flexibility and/or functionality of the circuitry on a chip exacerbates these challenges. Thus, what is needed is a tool with which integrated circuit designers can efficiently (i) route signals such that corresponding characteristics can be determined and/or estimated and (ii) size cells to better optimize power consumption, thereby facilitating timing closure in an automated place-and-route flow.